Hardware Reference
In-Depth Information
3.6.3
FSM Module
As introduced in Sect.
3.1
, automatic error recovery can be implemented by an FSM.
The input of the FSM is the detection results from sensing module. The outputs of
the FSM are the starting and ending storage addresses of the dictionary entry that
must be applied to the biochip. When the detection module sends a signal indicating
that an error has occurred, the FSM transits from one state to another state for error
recovery. The starting and ending storage addresses of the dictionary entry that will
be applied to the biochip are changed accordingly.
The output of the FSM is connected to the inputs of the ROM. When the
FSM sends the addresses of the dictionary entry, the data that are stored in the
corresponding memory cells are sent to the output of the ROM. As the data stored
in the ROM are the compacted dictionary entries, these data must be de-compacted
before that can be applied to the electrodes on the biochip. Therefore, the output
of the ROM is connected to the input of the de-compaction module, as shown in
Fig.
3.5
.
3.6.4
De-Compaction Module
The working principle of the de-compaction module is introduced in Sect.
3.5.2
.
The input of the de-compaction module is the compacted actuation sequence, and
the output is the de-compacted actuation signal sequence that can be directly applied
on the biochip.
The de-compaction modules that correspond to compaction Method I and
Method II are both implemented by the FPGA. When the working frequency of
the FPGA is set as 20 MHz, one dictionary entry with 930 elements, where each
element is an 8-bit binary number, can be decoded in less than 50 s. Therefore, the
time spent on dictionary de-compaction is negligible, when compared with the time
required to move a droplet from one electrode to an adjacent electrode.
3.6.5
Resource Report for Synthesized Modules
The modules are synthesized by Quartus II. The resource reports for the synthesized
droplet-tracking module and the de-compaction module are listed in Table
3.4
.The
FPGA resource occupied by the synthesized controller module depends on the total
number of states in the FSM. The relationship between the number of states and the
number of logic elements is shown in Table
3.5
. In the simulation, the actual FPGA
device selected by Quartus II is EP4CGX15BF14C6.
