Introduction - Hardware/Software Co-Design and Optimization for Cyberphysical Integration in Digital Microfluidic Biochips - page 14

Parametric faults may be caused by the following physical defects [ 34 ]:

• Geometrical parameter deviation: Due to the variations in the process, there

may exist deviations in the thickness of the insulator layer, the dimensions of
the electrodes, and the gap between the lower and upper plates. These deviations
may affect the accuracy of the fluidic handling operations [ 34 ].

• Insulator degradation: In the insulation layer, ionization and slot discharge

occur when the electrical field is high. The compounds formed during the
discharges and the bombardment of ions can degrade the nearby insulating mate-
rials. The degradation of the insulation layer may gradually become apparent
when the electrode performs fluidic operations. If the degradation of the insulator
is left undetected, it may eventually affect the functionality of the biochip [ 34 , 36 ].

• Particle contamination: When bioassays are executed on a biochip, the droplet

or the filler fluid on the biochip may be contaminated by dust particles or droplets
of a foreign fluid [ 34 ].

• Change in viscosity of droplet and filler medium: When unexpected biochemical

reactions occur on the biochip or the temperature varies in the biochip system,
the viscosities of part of the droplets and the filler medium may change [ 34 ].

1.2 Computer-Aided Design and Optimization

In recent years, design automation methods for digital microfluidics have received
significant attention [ 37 - 40 ]. This section discusses the research work that has been
published in this area.

1.2.1 Design Flow for Digital Microfluidic Biochips

A unified synthesis tool for digital microfluidic-based biochips is described in [ 41 ].
The tool can be used to map an abstract representation of the desired bioassay
protocol, e.g., a sequencing graph, into a design that can be implemented to
handle fluidic operations. The inputs of the synthesis tool are the bioassay protocol,
constraints imposed by the resources that are available on the biochip, and a library
of modules that can implement fluidic operations; the outputs are a mapping of assay
operations to on-chip resources and a schedule of the steps in the fluidic operations.
The synthesis procedure proposed in [ 41 ] includes architectural-level synthesis
and geometry-level synthesis. Architectural-level synthesis can be viewed as the
problem of scheduling fluidic handling operations and binding them to a given
number of resources, whereas geometry-level synthesis addresses the placement of
resources to satisfy area constraints. In [ 41 ], the parallel recombinative simulated
annealing (PRSA) algorithm forms the core of the synthesis procedure that is used
to obtain the optimized solution.