Hardware Reference
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Fig. 6.15
Pseudocode for determining the priorities of the movements of the droplets
6.7.1
Commercial Biochips
6.7.1.1
Commercial Biochip for
n
-plex Immunoassay
In an n-plex immunoassay, a sample is concurrently analyzed for n different
analytes. Sample droplets are mixed with n different reagents, and the mixed product
droplets are moved to the detection area which includes an optical detector [ 1 , 2 ].
The commercial biochip for the n-plex immunoassay consists of more than 1000
electrodes [ 1 , 2 ]. The layout of this biochip is shown in Fig. 6.16 a.
As seen in Fig. 6.16 a[ 2 , 13 ], the commercial chip for n-plex immunoassay is
based on a regular design that consist of two types of unit cells. We design the unit
cells in the layout and assign control pins for each unit cell; all other cells can be
assigned pins based on the same configuration. By applying the heuristic algorithm
proposed in Sect. 6.4 , we obtain the pin-assignment for the Type I and Type II unit
cells, as shown in Fig. 6.16 b and Fig. 6.16 c. Note here these two unit cells are
controlled by independent sets of pins, thus pins 1 to 7 are assigned to Type I unit
cell, and pins 8 to 18 are assigned to Type II unit cell.
Tab le 6.1 compares the existing pin-assignment configuration for the fabricated
commercial biochip [ 13 ], the result derived by bioassay-specific algorithm in [ 13 ],
and the result derived by the proposed heuristic method. The proposed heuristic
method leads to comparable or smaller number of control pins than both [ 13 ]andthe
fabricated commercial biochip. Since the pin-assignment derived by the proposed
method is bioassay-independent, it also provides the added benefit of being flexible
for multiple target applications.
The CPU time for designing the layout for the commercial biochip can be found
in Table 6.1 . The existing pin-assignment configuration is derived manually, so it
does not have CPU time [ 19 ]. The CPU time needed to generate the pin-assignment
configuration in [ 19 ] is 130 min. while the CPU time is reduced to 7.4 s for the
proposed heuristic algorithm.
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