Design of the Dynamic Supply CMOS RF Power Amplifie - Linear CMOS RF Power Amplifiers for Wireless Applications - page 32

into K> 1 at 5.2 GHz as shown by the case “with R stab1 ”inFig. 3.14 . However, at
frequencies lower than 5.2 GHz, the amplifier is potentially unstable.
A solution for ensuring stability at the lower frequencies consists of using a
shunt feedback with R stab2 and C stab from the drain of M 1 to its gate as depicted
in Fig. 3.13 . Due to the Miller effect, R stab2 and C stab appear in parallel with the
input and act like R stab1 , but for lower frequencies. C stab also prevents the gate
bias from being disturbed by the drain bias. The “with R stab1 , R stab2 , C stab ” case
in Fig. 3.14 shows that K> 1 at all frequencies. Hence, the amplifier is stable for
all possible combinations of passive source and load terminations. R stab1 and R stab2
were implemented with non-silicided polysilicon resistors, and C stab with a Metal-
Insulator-Metal (MIM) capacitor.

3.4 Dynamic Supply RF Power Amplifie

Besides the modulator and the PA, the dynamic supply system still requires a cou-
pler, an envelope detector, and an envelope processing block. These components are
not fundamental for the system if we consider the use of the dynamic supply PA in
an modern transceiver in which the envelope is directly available from the digital
baseband circuitry. However, for the system that we developed those components
are necessary to make it possible to test the circuit. To simulate the dynamic supply
PA in ADS, we used behavioral blocks to model these components. Experimentally,
as it will be seen in Chap. 4, they were replaced by the off-chip circuitry described
in that chapter.
The circuit simulated in ADS is shown in Fig. 3.17 . The values of the components
used are given in Table 3.1 . The component FDD2P is a 2-port, frequency-domain
defined, nonlinear device [ 2 ] used to detect the envelope of the input RF signal. It
also performs the analog envelope processing (gain and offset) together with the
component LimiterSML [ 3 ] (minimum and maximum voltage values). The result-
ing waveforms for the PWM and dynamic supply signals ( v sw and v out —refer to
Fig. 3.3 ) after a 2-tone test are depicted in Fig. 3.18 . The dynamic supply voltage
signal is the processed envelope with an offset and gain. It corresponds to an output
power of 11.9 dBm (15.5 mW), 61 mA rms current consumption (modulator and
PA), a gain of 4.9 dB, a PAE of 6.9%, and an IMD3 of 50 dBc. The minimum fre-

quency of the switching signal v sw —this frequency varies with the dynamic supply
voltage level—is approximately 24 MHz. This signal is well averaged by the LC fil-
ter and the ripple observed in the supply voltage is very low (maximum 30 mV pp ).
The tone spacing used in this simulation is 500 kHz and the LC filter cutoff fre-
quency is set to 1.62 MHz.
The LC filter, which is part of the modulator, and therefore not shown in
Fig. 3.17 , is designed according to the impedance ( Z PA ) seen by the modulator
when looking toward the PA. This impedance, which can be represented as a re-
sistance ( R p ) in parallel with a capacitance ( C p ), was simulated with ADS and the
result is shown in Fig. 3.19 .

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