Procedure for Impedance Matching of Printed-Circuit RF Amplifier - Linear CMOS RF Power Amplifiers for Wireless Applications - page 141

10.2.6 Summarized Guidelines
The list below summarizes the procedure described in this section and can be used
together with the flowchart of Fig. 10.2 as a quick reference guide.
1. Design and fabricate the PCB fixture with special attention to the input and out-
put microstrip access lines. TRL standards should be fabricated simultaneously.
2. Make SOLT calibration and measurement.
3. Make TRL calibration and measurement.
4. a. Model the fixture elements (embedding network).
b. De-embed the fixture elements from the SOLT measurement data.
c. Compare the resulting data with TRL measurement data to validate the em-
bedding network model.
5. a. Add the embedding network model to the TRL measurement data.
b. Virtually add capacitor(s) in shunt to the microstrip access lines in a position
that results in the desired matching.
c. Physically place the capacitor(s) on the PCB.
d. Make final SOLT measurement.
10.3 Application Example
To illustrate the procedure for impedance matching just described, this section
presents a real and practical example that involves the characterization of a 5.2 GHz
single-stage RF power amplifier integrated in a 0.11 µm CMOS technology.
10.3.1 First Step
The printed-circuit board for the evaluation of the RF PA is designed taking care
that a 50 transmission line of a length of at least λ/ 2 is present in the input and
output access lines from the SMA connectors to the input and output of the PA. The
chip-on-board method is used to mount the integrated PA onto the board. Hence,
the SMA connectors, the launchers onto which the connectors are soldered, and the
50 microstrip line form the access lines. In both sides of the 50 microstrip
lines, ground planes are created to facilitate the placement of 0402-case-size chip
capacitors in shunt to them. The possible PCB fixture shown in Fig. 10.1 is a repre-
sentation (not to scale) of the real fixture used in this example. The TRL standards
and the PCB were designed and fabricated at the same time.
10.3.2 Second Step
Figures 10.3 and 10.4 show the small signal S parameters S 11 (input reflection co-
efficient) and S 22 (output reflection coefficient), and Fig. 10.5 shows S 21 (forward