Procedure for Impedance Matching of Printed-Circuit RF Amplifier - Linear CMOS RF Power Amplifiers for Wireless Applications - page 136

is exhaustive for both parts of the matching process, only a few papers deal with the
two of them together [ 9 , 23 , 24 ].
O'Reilly, Neidert, and Wilson in [ 24 ] proposed a computer-aided procedure for
RF power amplifier matching in which an optimization routine provides the dimen-
sions of the microstrip sections for the on-board matching. The drawback of their
procedure is that the routine requires the knowledge of the impedance to be pre-
sented at the input and output of the amplifiers. These impedances are determined
with conductive tape overlays that are adjusted so that the desired performance can
be achieved.
Nickel and Schutt-Ainé in [ 23 ] presented a methodology for narrowband ampli-
fier design where chip capacitors are used to form matching networks in a coupled
microstrip system. The position and value of the chip capacitors are optimized via
software. The disadvantage of their approach is that the parameters of the transistor
are obtained through measurements using a separate fixture.
Choi, Youm, and Hwang in [ 9 ] developed an S-parameter extraction method for
PCB mounted RF amplifiers. The S parameters of the extracted transistor (or am-
plifier) are then used to design the impedance matching network. The drawback
of their procedure is that the design of an additional PCB to extract the transistor
S parameters is required.
A common drawback of these three approaches is the necessity of a dedicated
fixture to determine the value of a fundamental variable. In [ 24 ], this variable is the
impedance to be presented to the input/output of the amplifier, whereas in [ 9 , 23 ]it
is the set of S parameters of the amplifier.
With the objective of eliminating the need of a second board (or fixture), we
developed a new procedure for systematic impedance matching of printed-circuit
RF amplifiers. In this new procedure, no optimization is required, and the informa-
tion obtained with two-tier de-embedding techniques is used to implement on-board
matching networks assisted by the Smith chart.
The procedure is divided in five steps and a detailed description for each of them
is presented. Summarized guidelines are given for quick reference. A practical ex-
ample illustrates the application of these guidelines in the impedance matching of
a chip-on-board CMOS power amplifier operating at 5.2 GHz. The results are dis-
cussed and compared with previous works.
10.2 Procedure for Impedance Matching
Consider the characterization of an integrated RF power amplifier 1 bonded to a
printed-circuit evaluation board using the chip-on-board technique. The access to
the input and output terminals of this amplifier is made through microstrips that ar-
1 It could also be a commercial RF amplifier or transistor, but, in these cases, the matching difficul-
ties could be caused by the lack of information about package parasitics at the desired frequency.