Measurement Results for the Frequency-Tunable CMOS RF Power Amplifie - Linear CMOS RF Power Amplifiers for Wireless Applications - page 109

Fig. 7.14 Photograph of the
tunable RF PA chip bonded to
a printed-circuit board
visible. The integrated circuit occupies an area of 1.2 mm 2 (1200 µm per 1000 µm)
including the 14 pads used. Six of them are used for the ground connection. A high
number of ground pads is desirable to reduce the inductance between the chip and
PCB grounds. Although the VDD supply voltage is not directly connected to the
integrated circuit, as it arrives from the off-chip RF Choke, a VDD pad is used to
bias the deep n -well 2 with the highest DC voltage in the circuit.
In a similar way to the dynamic supply PA, the chip was lodged in a window
opened in the printed-circuit board in order to reduce the length of the bondwires
resulting from the chip-on-board mounting. Bondwires with 0.4 µm length could be
realized with this method, resulting in inductances of approximately 0.4 nanohenry
per bondwire, if we consider a value of 1 nH / mm [ 8 , p. 53]. (A more accurate
calculation of bondwire inductance can be done as described in [ 10 ].) This special
mounting procedure involved opening a window in the board and soldering a piece
of metal sheet at the bottom of the board below the window. The chip was inserted
in the window with its bottom attached to the metal sheet with a conductive glue.
This was done so as to connect the back of the chip to the ground plane of the
PCB (bottom layer). The PCB was fabricated using Rogers high-frequency laminate
RO4350 [ 14 ] whose main properties are given in Table 4.1 on p. 40.Thiskindof
laminate is distinguished for its stable electrical properties and low dielectric loss
(low tan δ [ 13 , Chap. 1]), which makes it suitable for the design of repeatable high-
frequency circuitry. To reduce the parasitic inductance in the ground lines, multiple
vias were used to connect the ground in the top layer of the PCB to the ground plane.
The test procedure was done in the following order:
1. Bias the PA at the desired quiescent point (through V bias1 ).
2. Bias the control circuit at the desired quiescent point (through V bias2 ).
3. Measure the S parameters and implement the input impedance matching.
2 In triple well processes, the deep n -well is used as an RF isolation strategy for n -type devices [ 4 ].