Advanced Methods for the Analysis of Semiconductor Manufacturing Process Data - Advanced Techniques in Knowledge Discovery and Data Mining - page 31

to take off. Meanwhile, also at Fairchild, a group of researchers 4 were getting a
handle on manufacturing stable metal-oxide semiconductor (MOS) field effect
transistors. They had actually been invented decades before the bipolar tran-
sistor, but irreproducible characteristics and fast degradation had prevented
their application. The MOS transistor came back into focus because as a sur-
face device it is a natural match to planar processing. In 1963 complementary
MOS, 5 or CMOS, now the dominant technology for ICs, was invented. In the
April 1965 issue of Electronics [2.40], Gordon Moore boldly predicted 6 that
the number of components per IC would double each year at least through
1975. Depending on how you count components, the actual doubling interval
turned out to be 18 months, but the general pattern of exponential growth
has proven to be accurate for more than 40 years, with no end in sight. One
of the important consequences is that the smallest feature

of an IC has
to be halved about every three years. The diminishing of the feature size is
commonly called technology scaling or shrinking, derived from the fact that
at larger feature sizes it su ced to simply draw the layout of an IC at a
smaller scale to go from one technology generation to the next (provided the
new technology was designed to be compatible with the old). As

F

becomes
smaller, it becomes more di cult, if not impossible, to keep this strict com-
patibility between technology generations; however, there are design tools to
“scale” IC layouts down to the new generation while making these differences
transparent. Technologies with an F of 0.13 µ m are in production right now,
and the next technology generation with sub-100-nm structures is imminent.
These ICs will integrate more than 100 million transistors.

F

2.2.2 IC Production Process

The prevalent technology for producing ICs today is CMOS on silicon. The
silicon substrate (called the wafer) is sliced off of a single crystal of extremely
pure silicon (the ingot) at a precise angle with respect to the cristallographic
orientation. The wafers are then polished to achieve an atomically smooth
surface and extreme flatness. Currently, wafer diameters of 200 mm are most
common, while 300 mm wafers just being put into production.
The actual IC production process takes place in clean rooms, at the so-
called fab floor. Clean rooms are classified by the number of particles larger
than a certain size in a cubic meter of air. A laminar flow of air from the
ceiling to the bottom is maintained to quickly remove any particles becom-
ing airborne. The IC production process is roughly divided into the wafer or
frontend processing, wafer test, and the back-end processing where the chips
are singulated, packaged, and subjected to more tests. Commonly test and

4 One of them was Andrew Grove, later to become Intel employee number 4.
5 Thus far, MOS IC technology had employed only n -conducting devices, which
led to the name NMOS technology.
6 In various forms, this prediction is now known as Moore's law. Beyond that
prediction, this article is an elucidating read even today, almost 40 years later.