PARTICLE FILTERING - Adaptive Signal Processing: Next Generation Solutions - page 324

In [11], a hardware designed with processing elements (PEs) and a central unit
(CU) was proposed. Each PE processes fractions of the particles (meaning particle
propagation and their weight computations) whereas the CU controls the PEs and per-
forms resampling. The resampling step represents a bottleneck in the parallel
implementation of the filter, and it introduces other disadvantages. It increases
the sampling period of the filter, that is, it slows down its operation, and it increases
the memory requirements of the filter. The resampling also entails intensive data
exchange within the filter, where large sets of data have to be exchanged through
the interconnection network. In brief, besides being a bottleneck, the resampling
step increases the complexity of the CU.
As pointed out, there are many implementation issues with particle filtering. One of
them is the development of resampling schemes which are better for hardware
implementation. For example, schemes that require less operations, less memory
and less memory access are desirable. It is also preferable to have a resampling
schemewith a deterministic processing time. Designs of algorithms that allow for over-
lap of the resampling step with the remaining steps are particularly desirable. Some
generic architectures for sampling and resampling are presented in [7]. GPFs do not
require resampling in the usual sense and they are better for parallel implementation.
The data exchange that is required for them is deterministic and is much lower than for
standard PFs, and they do not require the storage of particles between sampling
instants. Some of the implementations of GPFs proposed in [11] achieve speeds
twice that of standard PFs. The computation requirements of the GPFs are, however,
higher in that they need more random number generators and more multipliers.
Other issues include the use of fixed and floating point arithmetic and scalability.
The area and speed of the filter design depend on various factors including the number
of used particles and the levels of implemented parallelism.
Reconfigurable architectures for PFs have also been explored [8]. Since PFs can be
applied to many different problems, the idea is to develop architectures that can be
used for different problems and thereby allow for flexibility and generality. Namely,
designs on adaptable platforms can be configured for various types of PFs by modify-
ing minimal sets of control parameters. We can view this effort as the development of
programmable particle filtering hardware. One idea is to be able to select a PF from a
set of possibilities where all of the available filters have maximum resource sharing in
that the processing blocks are maximally reused, and the interconnection and interface
between them is carried out by distributed buffers, controllers, and multiplexers [8].
An example of a reconfigurable PF for real-time bearings-only tracking is presented
in [36]. Reconfigurability can include the type of used PF, the dimension of the
state spaces, and the number of employed particles.
5.12 ACKNOWLEDGMENTS
The work of the authors on particle filtering has been supported by the National
Science Foundation (Awards CCR-0220011 and CCF-0515246) and the Office of
Naval Research (Award N00014-09-1-1154).