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behavior (with the output register included) is similar to that of a pure Moore machine
(without the output register—see details in section 3.5).
5.3 Number of Flip-Flops
In general, and particularly in large designs, it is difi cult to estimate the number of
logic gates that will be needed to implement the desired solution. However, it is always
possible to determine, and exactly , the number of l ip-l ops.
In the case of sequential circuits implemented as category 1 state machines, there
are two demands for DFFs, as follows (see state-encoding options in section 3.7).
1) For the state register (see nx_state and pr_state in i gure 5.2a, which are the state
memory l ip-l ops' input and output, respectively; below, M FSM is the number of states):
For sequential or Gray encoding: N FSM = log 2 M FSM . Example: M FSM = 25
N FSM = 5.
For Johnson encoding: N FSM = M FSM /2 . Example: M FSM = 25
N FSM = 13.
N FSM = 25.
2) For the output register (i gure 5.2c, optional, with b output bits):
N output = b output . Example: b output = 16
For one-hot encoding: N FSM = M FSM . Example: M FSM = 25
N output = 16.
Hence, the total is N total = N FSM + N output . In the examples that follow, as well as in the
actual designs with VHDL and SystemVerilog, the number of l ip-l ops will be often
examined.
5.4 Examples of Regular (Category 1) Machines
A series of regular FSMs are presented next. Several of these examples are designed
later using VHDL (chapter 6) and SystemVerilog (chapter 7).
5.4.1 Small Counters
Counters are well-known circuits easily designed without the FSM approach using
VHDL or SystemVerilog. Moreover, a counter might have thousands of states, render-
ing it impractical for representation as a regular state machine. Nevertheless, for
designing counters without the help of any EDA tool (as done in sections 3.3 and 3.4),
the FSM model can be very helpful, particularly if the counter is not too big and has
several control inputs such as enable and up-down. Moreover, the implementation of
such counters can be very illustrative of the FSM approach. For these reasons, an
example is included in this section.
A 1-to-5 counter with enable and up-down controls is presented in
i gure 5.3 (just
to practice, equivalent detailed and simplii ed representations are shown—recall i gure
1.4). The circuit counts if ena = '1', or stops (and holds its last output value) otherwise.
If up = '1', the circuit counts from 1 to 5, restarting then automatically from 1; oth-
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