Hardware Reference
In-Depth Information
4.3 Design Steps Summary
We close this chapter by summarizing the main steps that should be observed in
designing sequential circuits using the FSM approach.
1)
Specii cations analysis:
Study the problem specii cations carefully. As a i nal step,
decide:
a) The FSM category (regular, timed, or recursive) to be adopted.
b) The FSM type (Moore or Mealy) to be used.
c) Whether the optional output register should be included.
2)
State transition diagram:
Based on your analysis and conclusions above, carefully
draw the state transition diagram. The use of a detailed diagram (as in i gure 1.4d) is
particularly recommended in complex designs or for beginners because it helps visual-
ize and assure that all transition conditions have been completely and correctly
covered.
3)
Encoding style and resources usage:
Decide which state-encoding option (e.g.,
sequential, Gray, Johnson, one-hot) will be employed in the design. After that, the
exact number of DFFs that will be needed to build the FSM can be calculated. Do it,
so your estimate can be compared later against the actual number reported by the
VHDL/SystemVerilog compiler (this is a very important checkpoint).
4)
Reset signal:
Analyze your FSM and decide whether an explicit reset port is needed.
Recall that, as seen in sections 3.8 and 3.9, only occasionally is a state machine guar-
anteed to work properly without a dedicated reset signal.
5)
Input signals:
Two fundamental features must be observed with respect to the
input signals. The i rst regards the aspect of such signals. For example, they might
have glitches, or they might be too short or too long, so proper signal conditioning
might be required. The second regards synchronism. If any input is asynchronous with
respect to the FSM, analyze if metastability (section 2.3) can be critical to the applica-
tion. If that is the case, and no other part of the circuit is taking care of metastability,
add a synchronizer for each asynchronous input from which the machine must be
protected. Do not forget to take into account the latency that this will cause.
6)
Code and compilation:
Write the corresponding VHDL/SystemVerilog code and
synthesize it (design by hand is viable only for very simple circuits). Compare the
number of l ip-l ops inferred by the compiler against your prediction.
7)
Simulation:
Fully simulate your design (graphically or, preferably, with VHDL/
SystemVerilog testbenches). If the simulation is too time consuming, do functional
simulation i rst until the design is debugged; then do timing simulation.
8)
Physical implementation:
Finally, download the resulting FPGA programming i le
(.pof or .sof) into the physical device in order to program it and proceed to the physi-
cal tests.
