Hardware Reference
In-Depth Information
underspecii cation would occur, and the compiler might again infer unnecessary (and
undesirable) latches.
4.2.9 Overregistered VHDL/SystemVerilog Code
This is another common mistake. It is very important to be aware of the code sections
that infer registers and close such sections as soon as registers are no longer needed.
An example is shown below, using VHDL. Any signal to which a value is assigned
under the
if rising_edge(clk)
statement will be registered, so that
if
must be closed
as soon as possible. The code on the left is constructed correctly. Note that the only
assignment under the
if rising_edge(clk)
statement is
pr_state
= nx_state
, so only
the machine state gets registered. Because the
case
statement used for the upper
section is outside that
if
statement, no l ip-l ops will be inferred for that part of the
machine, resulting in a truly combinational circuit for the upper section, which is
how it should be.
The code on the right, on the other hand, is an example of an error-prone design.
Note that now the
case
statement is inside the
if rising_edge(clk)
statement, so the
output will also be registered. As we have already seen, there are cases in which the
optional output register is needed, but that is a case-by-case decision, not a forced
condition as it is in this code. Probably the worst aspect of this code is that the designer
might be completely unaware of what is actually happening. (Note that
pr_state
has
no effect in this process' sensitivity list.)
<
--Good:
--Error prone:
--lower section of FSM:
process (clk, pr_state)
process (clk)
begin
begin
if rising_edge(clk) then
if rising_edge(clk)then
--lower section of FSM:
pr_state <= nx_state;
pr_state <= nx_state;
end if;
--upper section of FSM:
end process;
case pr_state is
--upper section of FSM:
when A =>
process (all)
output <= <value>;
begin
if <condition> then
case pr_state is
nx_state <= B;
when A =>
else
output <= <value>;
nx_state <= A;
if <condition> then
end if;
nx_state <= B;
when B =>
else
...
nx_state <= A;
end case;
end if;
end if;
when B =>
end process;
...
end case;
end process;
