Hardware Reference
In-Depth Information
4.2.6 Lack of Synchronizers
Many FSMs have asynchronous inputs, so metastability can occur if synchronizers are
not employed. Failing to analyze whether asynchronous signals are involved in the
design and the possible consequences of metastability to that particular application
can compromise the entire project. Material on the use and construction of synchro-
nizers and their consequences was presented in section 2.3.
4.2.7 Incorrect Timer Construction
Many engineering problems include timed decisions, leading to state machines
with time as a transition condition (see i gure 1.8). Because timers are just counters
(therefore sequential circuits, which can then also be modeled as state machines),
one might be tempted to use the FSM approach to design them. There are two main
reasons for not doing so in general. The i rst is that counters are standard circuits,
easily designed without the FSM approach. The second is that a counter might
have thousands of states and therefore would be impractical to represent as a
regular
state machine.
The recommended approach in such cases is to consider the timer (counter) as an
auxiliary circuit, implemented separately and acting as an
input
to the (main) state
machine. However, the state machine itself must be responsible for clearing the timer
at the proper moments as well as for stopping it or letting it run as needed. Such i ne
details, sometimes overlooked, are fundamental to attain a correct and optimized
design. Such aspects are studied in chapter 8, which deals specii cally with timed state
machines, and are reinforced in chapters 9 and 10, which show VHDL and System-
Verilog implementions for timed FSMs.
4.2.8 Incomplete VHDL/SystemVerilog Code
Once the state transition diagram has been correctly and completely constructed, we
can write a corresponding VHDL or SystemVerilog code to synthesize the circuit. The
problem is that here too the coverage of specii cations might not be complete, even
if the state diagram is complete. Two common mistakes are described below, both
related to the combinational logic section of the FSM (more precisely, related to req-
uisites 2 and 3 listed in section 4.2.3).
The i rst mistake regards incomplete
output
specii cations. One might believe that
when something was said in a previous state and nothing occurred there is no need
to say it again. For example, consider that we are using VHDL and the
case
statement
to implement the combinational logic section of an FSM as follows (do not worry
about code details for now; they are seen in chapter 6):
--Bad:
--Good:
case pr_state is
case pr_state is
when A =>
when A =>
