Hardware Reference
In-Depth Information
more elaborate CPU instructions. Several examples with multiple machines are seen
in chapters 8 and 11.
3.13 State Machines for Datapath Control
The purposes of this section are to review datapath-related concepts and to describe
how state machines can be used to build the
control unit
that controls a datapath.
Because the control unit is generally the most complex circuit to design in this kind
of application, and the FSM approach is employed to do it, a study of state machines
for datapath control is indispensable.
A popular datapath is that of microprocessors and microcontrollers, needed to
construct the CPU, write/read data to/from memory, communicate with peripherals,
and so on. Fundamental components for datapath construction are depicted in i gure
3.21. Note that they all have some type of control input (
sel
,
ALUop
,
wrR
,
rdM
,
wrM
,
wrPC
,
wrIR
).
Multiplexers are digital switches used to route data from one location to another;
in the case of i gure 3.21, when the selection (
sel
) input is '0', the upper input is passed
to the output, whereas a '1' causes the lower input to be passed to the output. The
arithmetic logic unit (ALU), as the name says, is responsible for executing arithmetic
(+,
, *, /, …) and logic (AND, OR, XOR, …) operations; the operation is selected by
the ALU's operational code,
ALUop
. Registers are simply DFF banks: for example, a
32-bit register is simply a set of 32 parallel DFFs; note the write-register (
wrR
) input,
which must be asserted for the input data to be stored into the DFFs (at the next posi-
tive clock edge). The data memory is used to store data during datapath operations;
it contains two control inputs, for reading from (
rdM
) or writing into (
wrM
) the
−
Figure 3.21
Main datapath components.
