Hardware Reference
In-Depth Information
3.7.6 Other Encoding Schemes
Besides the encoding schemes described above, VHDL and SystemVerilog synthesis
compilers have at least two other options, known as
user
and
auto
. The former is a
user-dei ned encoding (the codeword for each state is specii ed by the user), whereas
the latter is used to let the compiler choose the best encoding scheme based on the
target device. Typically,
auto
employs sequential encoding for small machines (for
example, up to four or i ve states), then one-hot for medium-sized machines (for
example, up to 40 or 50 states), and i nally sequential again (or an equivalent, such
as Gray) for larger machines. In general,
auto
is the compiler's default option.
The one-hot style is common in applications where l ip-l ops are abundant, such
as i eld programmable gate arrays (FPGAs), whereas minimal-bit encodings (such as
sequential and Gray) are common in complex programmable logic devices (CPLDs)
and in compact, low-cost application-specii c integrated circuits (ASICs).
Chapters 6 and 7 show how to select the encoding scheme when using VHDL or
SystemVerilog, respectively.
3.8 The Need for Reset
If no reset signal is provided and no intentional circuit asymmetry exists (such that
a specii c output state is favored), the initial state (output either low or high) of a
l ip-l op, on power-up, might be arbitrary. Because l ip-l ops are used to construct
the state register, the machine's initial state would then also be arbitrary. In this
case, one of two situations will result: either the initial state is
internal
(that is,
belongs) to the machine or is
external
(does not belong) to it. Of course, if
N
bits
are used to encode a machine that has 2
N
states, then the initial state can only
belong to the machine.
When the initial state is internal, deadlock can still happen, but only in rare cases,
so the usual main consequence is a possibly undesirable sequence of events during
the i rst few state transitions. If the initial state is external, however, deadlock is much
more likely, obviously in addition to the possibly undesirable sequence of events
during the i rst few state transitions after the system converges to one of the FSM
states (assuming that deadlock has not occurred).
To further illustrate this discussion, let us consider the four-state counter of i gure
3.11a, whose states are encoded using one-hot code (the corresponding
pr_state
=
q
3
q
2
q
1
q
0
vectors are shown below the state circles). The equations for
nx_state
=
d
3
d
2
d
1
d
0
can be easily obtained using the method described in section 3.3, resulting
d
3
=
q
2
,
d
2
=
q
1
,
d
1
=
q
0
, and
d
0
=
q
3
. Consequently, if the initial state is
q
3
q
2
q
1
q
0
= “0000”, for
example,
d
3
d
2
d
1
d
0
= “0000” results; because
nx_state
=
pr_state
, a deadlock then occurs.
Indeed, based on the equations above, note that with one-hot encoding any time the
initial state falls outside the FSM the machine gets deadlocked.
