Hardware Reference
In-Depth Information
i gure 3.7b. The input
sequence is again
x
= {'0', '1', '0', '1', '0', '1', '0', '0'}. Following the state transition
diagram of i gure 3.6a, the sequence obtained for the present state is
pr_state
= {B,
C, A, A, B, C, A, B}. As shown in the state diagram, the output is '0' in states A and
B, and it is
x
A similar analysis is presented for the Mealy circuit in
in state C, thus resulting (after a small propagation delay) in the output
sequence
y
= {'0',
x
′
, '0', '0'}. Note that
x
appears in the list for
y
,
which was expected because in a Mealy machine the input can affect the output
directly. For the same reason, this machine is asynchronous (note that in state C,
y
changes independently of the clock). Observe also that, because it is asynchronous,
the shape of
y
can be quite strange, with values lasting less than one clock period.
On the other hand, observe the interesting shape of
y_reg
, which is exactly the same
as the shape of
y
in the Moore case. This means that when we want to get rid of
glitches and the consequent extra delay of an out-registered (pipelined) Moore
machine is not acceptable in the application, an out-registered (pipelined) Mealy
machine can be used.
Another drawback of the original Mealy machine is that input glitches can propa-
gate to the output, as depicted in the plot for
y
in i gure 3.7b.
′
, '0', '0', '0',
x
′
3.6 State Machine Categories
We have already seen that state machines can be classii ed into two types, based on
their
input connections
, as follows.
1)
Moore machines:
The input, if it exists, is connected only to the logic block that
computes the next state.
2)
Mealy machines:
The input is connected to both logic blocks, that is, for the next
state and for the actual output.
In this section we introduce a new classii cation, into three categories, based on
the
transition types
and
nature of the outputs
.
As mentioned in section 1.2 (see Hardware- versus Software-Implemented State
Machines), designing a hardware-implemented FSM is generally (much) more complex
than designing a software-implemented FSM. To ease such a task, a very important
new classii cation, from a hardware perspective and covering
any
state machine, is
introduced here (this classii cation dictates the organization of the subsequent chap-
ters). Figure 3.8 is used as an illustration.
Category 1: Regular (pure) state machines
(studied in chapters 5-7): This category, illus-
trated in i gure 3.8a, is the simplest. It consists of machines with only untimed transi-
tions and outputs that do not depend on previous (past) output values.
Category 2: Timed state machines
(studied in chapters 8-10): These consist of machines
with one or more transitions that depend on time, but still having only outputs that
