Hardware Reference
In-Depth Information
Figure 3.5
Simulation results from the nonoverlapping “010” detector of i gure 3.4e (Moore type).
to render a glitch-free
y
. (Recall the comments made earlier on increased latency and
possible use of a Mealy machine in this kind of situation.)
Simulation results from the circuit of i gure 3.4e, without the extra DFF, synthesized
using VHDL, are shown in i gure 3.5. Note the following (expected) results:
1) The output changes only at (positive) clock edges (Moore machines are
synchronous).
2) The output goes to '1' at the i rst (positive) clock edge after the sequence “010”
occurs.
3) Overlaps do not cause the output to go to '1'.
4) Without the optional output DFF, glitches do occur at the output.
3.4 Fundamental Design Technique for Mealy Machines
This section describes a fundamental design technique for Mealy machines. It is a “by
hand” design; in the succeeding chapters, the designs are developed with VHDL and
SystemVerilog.
As seen above, from a hardware perspective a Mealy machine can be represented
as in i gures 3.2a,b with both input connections (1 and 2). The corresponding design
procedure is the same seen for Moore machines, with just one difference, in step 2,
as follows.
Step 2:
Based on the state diagram,
write a single truth table
, including both the next
state and the output. Then rearrange the truth table . . . etc.
If the Moore-to-Mealy conversion technique introduced in section 1.7 is applied to
the Moore diagram of i gure 3.4a, the Mealy diagram of i gure 3.6a results. Its truth
table (including both
nx_state
and
y
) is shown in i gure 3.6b. From this table, the
