Hardware Reference
In-Depth Information
Figure 3.2
FSM architectures and input connection options.
5) The upper section has two inputs. That called
input
is external and, depending on
the application, might not exist (as in the example of i gure 1.2b). That called
pr_state
is internal and mandatory.
6) There are three input options (i gure 3.2c): with no external input (Moore); with
the input connected only to the
nx_state
logic block (connection 1; Moore); and with
the input connected to both logic blocks (connections 1 and 2; Mealy).
7) Finally, note the extra register at the output (i gure 3.2b) for glitch removal or
pipelined implementation.
3.3 Fundamental Design Technique for Moore Machines
This section describes a fundamental design technique for Moore machines. It is a “by
hand” design; in the succeeding chapters, the designs are developed with VHDL and
SystemVerilog.
As seen above, from a hardware perspective a Moore machine can be represented
as in i gures 3.2a,b, but having only connection 1 or no external input at all (except,
of course, for clock and reset). The corresponding design procedure, consisting of i ve
steps, is summarized below. The i rst four steps relate to the FSM proper, and the last
step regards the optional output register.
Step 1:
Draw the state transition diagram.
Step 2:
Based on the state diagram, write two truth tables, one for the next state
and the other for the output. Then rearrange the truth tables, replacing the state
names with signal names (
q
for l ip-l op outputs,
d
for l ip-l op inputs) and using
corresponding binary values. To do this, choose i rst the encoding style (described in
section 3.7).
