Hardware Reference
In-Depth Information
3 Hardware Fundamentals—Part II
3.1 Introduction
This chapter is a continuation of the previous chapter. It completes the study of fun-
damental hardware-related aspects that are essential to fully understand and correctly
design i nite state machines in hardware. Whereas chapter 2 dealt mainly with regis-
ters, chapter 3 deals with the complete state machine structure.
The topics seen in these two chapters are used, reinforced, and expanded as the
subsequent chapters unfold, particularly in chapters 5 (theory for category 1 machines),
8 (theory for category 2 machines), and 11 (theory for category 3 machines).
3.2 Hardware Architectures for State Machines
State machines are looped circuits, as already illustrated in i gure 1.2a. They can be of
Moore or Mealy type, depending on how the input is connected to the combinational
logic blocks. We want to verify here how FSMs are related to the pipeline models
described in section 2.6.
Figure 3.1a shows a Moore machine, characterized by the fact that the input is
connected only to block L
1
(recall that L
1
and L
2
represent logic blocks and that R
1
and R
2
are registers). Note the feedback loop from R
1
to L
1
, which is the most funda-
mental characteristic of any FSM. Observe also that the machine itself contains only
the L
1
-R
1
-L
2
stages, so if a full pipeline is desired, the optional register R
2
must be added.
An equivalent representation is shown in i gure 3.1b; the purpose of this arrangement
is to emphasize the feedback loop.
Figure 3.1c shows a Mealy machine, characterized by the fact that the input is
now also connected to block L
2
. Note that again the machine itself contains only the
L
1
-R
1
-L
2
stages. An equivalent representation is shown in i gure 3.1d, again emphasiz-
ing the feedback loop.
The optional output register can be used to obtain a fully pipelined implementation
with better time predictability and higher clock speed or for glitch removal, as seen
