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Figure 2.22
Figure 2.23
a) Draw the corresponding timing response in the lower part of the i gure, where i 1
and i 2 represent internal signals. Consider that the vertical lines are 1 ns apart and,
for sketching purposes, that L 1 and L 2 are just buffers.
b) After how many positive clock edges does the input pulse reach each output?
c) Which output ( outp1 or outp2 ) is fully pipelined? Which has superior time predict-
ability? Why?
Exercise 2.7: Glitch-free Clock Gater
All four possible clock-gating cases are depicted in i gure 2.23. Cases 1 and 2 relate to
FSMs operating at the positive clock edge, whereas cases 3 and 4 are related to FSMs
operating at the negative clock edge. In cases 1 and 3, the clock, when interrupted, is
replaced with a zero, whereas in cases 2 and 4, it is replaced with a one.
a) Asynchronous and synchronous solutions were discussed/developed for cases 1 and
3 (see i gure 2.8). Do the same for cases 2 and 4.
b) Can you devise other solutions (different from those presented in the topic) for
cases 1 and 3?
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