Hardware Fundamentals — Part I - Finite State Machines in Hardware - page 32

Figure 2.15
Glitch interpretation (bits must be examined individually).

signal. As a i nal remark, observe that this technique is not OK when there are signal
transitions at both clock edges, as in i gure 2.13b, but that is not the case in state
machines, so for FSMs this technique is i ne.
We conclude this section by calling attention to a confusion that often occurs in
inspecting simulation or measurement results. This is illustrated in i gure 2.15, which
shows a timing diagram for a three-bit counter. Because count is formed by more than
one bit, it might exhibit glitch-like information. This, however, does not mean that
actual glitches have occurred. Recall that two physical signals, due to different propa-
gation delays, will never change exactly at the same time (and they are not perfect
voltage steps anyway), so the value of count is expected to go through intermediate
values before reaching the i nal value. As an example, in the inset of i gure 2.15 count
goes through 3 4 instead of moving straight from 3 to 4, even though

glitches have not occurred. In conclusion, to inspect glitches, we must examine only
one bit at a time.

→ 2 → 0 →

2.6 Pipelined Implementations

Figure 2.16a shows a common architecture for high-speed synchronous systems. Each
circuit—possibly designed by a different team or from an IP (intellectual property)
cell—is constructed in RTL (register transfer logic) fashion, resulting in a pipelined
implementation. In other words, combinational logic blocks (L 1 , L 2 , etc.) are followed/
separated by registers (R 1 , R 2 , etc.) (registers are just DFF banks). The advantage of
having a register as the i nal stage element is that the time behavior of DFFs is well
known, so the overall timing response can be safely predicted, allowing the clock speed
to be maximized.
To illustrate this, say that circuit 2 is constructed using only L 2 -R 2 -L 3 . In this case,
after a clock edge occurs, the total output propagation delay will be that through R 2
( t pCQ of i gure 2.3a) plus that through L 3 . However, contrary to R 2 , whose construction
and parameters are known in advance, L 3 varies from one design to another and with
the routing, making the time response more difi cult to predict. Because the absence
of R 2 increases the stage's propagation delay, the maximum clock speed gets reduced.