Hardware Reference
In-Depth Information
Figure 2.11
Glitch types.
Figure 2.12
(a) Combinational circuit implementing the function
y
=
a
⋅
c
+
b
⋅
c
′. (b) Corresponding Karnaugh
map. (c) Glitch generation when moving from
abc
= “111” to
abc
= “110”. (d, e) Glitch eliminated
by the addition of a redundant implicant.
Even though glitches are not a problem in many designs, it is important to be aware
of their existence and understand how they can be eliminated when that is necessary.
An example in which glitches can be disastrous is when a signal is used as a clock
because then the associated l ip-l ops can be (improperly) triggered by the glitches.
Figure 2.11 shows the glitch types, which can be static (single pulse) or dynamic
(multiple transitions). A static glitch is said to be of type static-0 when the signal
should remain stable at '0' but a pulse toward '1' occurs. The meaning of static-1
glitches is analogous.
An example of a circuit subject to glitches is presented in i gure 2.12a, which imple-
ments the function
y
=
a
⋅
c
+
b
⋅
c
′. The corresponding Karnaugh map is shown in i gure
2.12b, where two prime implicants can be observed. Although the value of
y
is '1' for
both
abc
= “111” and
abc
= “110”, when the input transitions from the former to the
latter, the involved propagation delays can produce a glitch at the output. This is
illustrated in i gure 2.12c, with
a
and
b
i xed at '1' and
c
changing from '1' to '0' (for
simplicity, it was considered that the propagation delays of all gates are equal). Figure
2.12e shows a solution for this problem, which consists of including a redundant
implicant covering the transition mentioned above, thus resulting in the circuit of
i gure 2.12d.
