Hardware Reference
In-Depth Information
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--Generate 5MHz clock for SPI circuit:
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process (clk)
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variable counter1: natural range 0 to 5;
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begin
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if rising_edge(clk) then
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counter1:= counter1 + 1;
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if counter1=5 then
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spi_clk <= not spi_clk;
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counter1:= 0;
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end if;
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end if;
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end process;
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--FSM (complete SPI circuit):
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process(spi_clk, rst)
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variable i: natural range 0 to 75;
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variable j: natural range 0 to 7;
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begin
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--Pointers (i, j):
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if rst='1' then
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i:= 0;
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j:= 0;
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elsif falling_edge(spi_clk) then
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if (i=0 and wr='0' and rd='0') or (i=42 and wr='0') or
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(i=75 and rd='0') then
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i:= 0;
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elsif(i=0andwr='1')or(i>0andi<34)or(i>=43andi<67)then
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i:= i + 1;
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elsif i=0 and rd='1' then
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i:= 43;
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elsif (i>=34 and i<=41) or (i>=67 and i<=74) then
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if j/=7 then
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j:= j + 1;
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else
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j:= 0;
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i:= i + 1;
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end if;
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end if;
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end if;
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--LUT (for outputs):
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--Default values:
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SSn <= '0';
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SCK <= spi_clk;
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MOSI <= '-';
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--Other values:
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case i is
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when 0 =>
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SSn <= '1';
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SCK <= '0';
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when 1 to 8 =>
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MOSI <= WREN_opcode(8-i);
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when 9 =>
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SSn <= spi_clk;
