Hardware Reference
In-Depth Information
A VHDL code for this machine is presented below (function
hex-to-ssd
not shown—
bring the package
my_functions
, from section 14.3.3, to your design). This code is
equivalent to that in section 14.3.3, except for a small difference in the test circuit
(here the stored values are sent to the display continuously). The entity (lines 6-22)
is the same as that in section 14.3.3, and so are the list of declarations for the SPI and
test signals (lines 27-32) and the
spi_clk
generator (lines 40-50). The FSM, constructed
using the pointer-based technique, is in the process of lines 53-115, with the pointers
built in lines 59-78 and the LUT in lines 82-113. Note in lines 108-110 that the
received data is stored in the
data_in
array while the machine is in the
rd_data
state.
The i nal part of the test circuit (data storage was embedded in the LUT) is in the
process of lines 118-140 (see comments in section 14.3.3).
1 --Maincode:---------------------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 use work.my_functions.all; --package from sec. 14.3.3
5 ---------------------------------------------------------------------------
6 entity FRAM_with_SPI_bus is
7 generic (
8 --Device's SPI parameters:
9 WREN_opcode: std_logic_vector(7 downto 0):= "00000110";
10 WRITE_opcode: std_logic_vector(7 downto 0):= "00000010";
11 READ_opcode: std_logic_vector(7 downto 0):= "00000011";
12
initial_addr_for_wr: std_logic_vector(15 downto 0):= (others=>'0');
13
initial_addr_for_rd: std_logic_vector(15 downto 0):= (others=>'0'));
14 --Assumed: fclk=50MHz, desired SPI speed=5MHz
15 port (
16 --System ports:
17 rd, wr, clk, rst: in std_logic;
18 ssd1, ssd2: out std_logic_vector(6 downto 0);
19 --SPI ports:
20 SCK, SSn, MOSI, WPn, HOLDn: out std_logic;
21 MISO: in std_logic);
22 end entity;
23 ---------------------------------------------------------------------------
24 architecture pointer_based of FRAM_with_SPI_bus is
25
26
--Clock for SPI and test signal declarations:
27
signal spi_clk: std_logic;
28
type data_array is array (0 to 7) of std_logic_vector(7 downto 0);
29
constant data_out: data_array:=
30
("00000001", "00100011", "01000101", "01100111",
31
"10001001", "10101011", "11001101", "11101111");
32
signal data_in: data_array;
33
34 begin
35
36
WPn <= '1';
37
HOLDn <= '1';
38
