Additional Design Examples - Finite State Machines in Hardware - page 316

b) Draw the state transition diagram for a second circuit, which should implement an
LCD driver to have the reference value displayed on an alphanumeric LCD.
c) Implement the complete circuit using VHDL or SystemVerilog and test it in the
FPGA development board.
Exercise 14.2: I 2 C Interface for an RTC
Repeat the design of section 14.2.5, this time with a category 2 machine instead of a
category 3.
Exercise 14.3: I 2 C Interface for an EEPROM
Develop an experiment (as in section 14.2.5), including VHDL or SystemVerilog code
and physical implementation in the FPGA development board, for a master circuit
that interfaces with an EEPROM device through an I 2 C bus. The device can be, for
example, AT24C01 or AT24C02, from Atmel.
Exercise 14.4: I 2 C Interface for an ADC
Develop an experiment (as in section 14.2.5), including VHDL or SystemVerilog code
and physical implementation in the FPGA development board, for a master circuit
that interfaces with an analog-to-digital converter through an I 2 C bus. The device can
be, for example, AD7991, from Analog Devices, or PCF8591, from NXP.
Exercise 14.5: I 2 C Interface for a Temperature Sensor
Develop an experiment (as in Section 14.2.5), including VHDL or SystemVerilog code
and physical implementation in the FPGA development board, for a master circuit
that interfaces with a temperature sensor through an I 2 C bus. The device can be, for
example, LM75A, from NXP, or AD7416, from Analog Devices.
Exercise 14.6: I 2 C versus SPI
Make a brief comparison between I 2 C and SPI interfaces. Include at least the following
topics in your analysis: synchronous or asynchronous, number of wires, duplex or
simplex, with data acknowledgment or not, which hardware is simpler and why, who
generates clock and data, which operates at higher speed.
Exercise 14.7: SPI Interface for a FRAM
Repeat the design of section 14.3.3, this time with a category 3 machine instead of a
category 2.
Exercise 14.8: SPI Interface for an ADC
Develop an experiment (as in section 14.3.3), including VHDL or SystemVerilog code
and physical implementation in the FPGA development board, for a master circuit