Hardware Reference
In-Depth Information
122
when deselect =>
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SSn <= spi_clk;
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SCK <= '0';
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nx_state <= WRITEx;
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when WRITEx =>
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MOSI <= WRITE_opcode(7-i);
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imax <= 7;
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if i=imax then
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nx_state <= initial_addr_wr;
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else
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nx_state <= WRITEx;
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end if;
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when initial_addr_wr =>
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MOSI <= initial_addr_for_wr(15-i);
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imax <= 15;
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if i=imax then
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nx_state <= wr_data;
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else
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nx_state <= initial_addr_wr;
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end if;
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when wr_data =>
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MOSI <= data_out(j)(7-i);
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imax <= 7;
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jmax <= 7;
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if i=imax and j=jmax then
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nx_state <= wait_wr0;
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else
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nx_state <= wr_data;
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end if;
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when wait_wr0 =>
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SSn <= '0';
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SCK <= '0';
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if wr='0' then
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nx_state <= idle;
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else
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nx_state <= wait_wr0;
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end if;
159
--Data-read sequence:
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when READx =>
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MOSI <= READ_opcode(7-i);
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imax <= 7;
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if i=imax then
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nx_state <= initial_addr_rd;
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else
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nx_state <= READx;
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end if;
168
when initial_addr_rd =>
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MOSI <= initial_addr_for_rd(15-i);
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imax <= 15;
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if i=imax then
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nx_state <= rd_data;
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else
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nx_state <= initial_addr_rd;
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end if;
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when rd_data =>
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imax <= 7;
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jmax <= 7;
