Additional Design Examples - Finite State Machines in Hardware - page 310

The entity, called FRAM_with_SPI_bus , is in lines 6-22. The SPI parameters were
declared as generic constants (lines 9-13). The circuit ports (lines 15-21) follow i gure
14.19a and are all of type std_logic or std_logic_vector (industry standard).
The architecture, called moore_fsm , is in lines 24-224. As usual, it contains a declara-
tive part and a statements part, both commented on below.
The declarative part of the architecture (lines 26-41) contains FSM-related and
timer-related declarations plus other system declarations. In the FSM declarations
(lines 27-29), the enumerated type state is created to represent the machine's present
and next states. In the timer declarations (lines 32-33), the signals needed to build
the timers i and j are created. Finally, the other declarations (lines 36-41) include the
SPI clock, plus a 1D 1D type called data_array used to build a ROM called data_out

(lines 38-40) whose contents are sent to the FRAM. A similar 1D

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1D signal is declared
in line 41, which is used to create a register in which all data read from the FRAM is
stored during the tests.
The statements part (lines 43-224) contains i ve processes. The i rst process (lines
49-59) creates the SPI clock (5 MHz, assuming that the system clock is 50 MHz; as
mentioned, this FRAM can operate at up to 20 MHz). As seen in i gure 14.17, this is
the only clock needed in the entire SPI circuit. Because the slave stores data at the
rising clock edge, the FSM (and therefore its associated timers too) must operate at the
negative edge.
The second process (lines 62-80) implements the timers. In this example, the timer-
control strategy #1 (section 8.5.2) was adopted.
The third process (lines 83-90) implements the FSM state register. Like the timers,
it too operates at the negative clock edge.
The fourth process (lines 93-193) implements the entire combinational logic
section. It is just a list of all states, obeying the state transition diagram of i gure 14.20
exactly. As usual, in each state the outputs ( SSn , SCK , MOSI ) and the time parameters
( i max , j max ,) are specii ed, and the next state is dei ned. Note that because some of
the output values are repeated a number of times, default values were entered in
lines 96-100, so the actual list of outputs and time parameters is exactly the same in
all states.
The i fth and i nal process (lines 196-223) builds the test circuit. First, the data
read from the FRAM (while the machine is in the rd_data state) is stored into
the data_in 1D

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1D register (at the positive clock edge, line 201, because the slave places
the data on the MISO wire at the negative clock transition). Because the machine
operates at 5 MHz, an independent slow counter (2 Hz) is produced in lines 205-214,
which allows the read data to be sequentially displayed on two SSDs while the machine
remains in the wait_rd0 state (that is, while the rd switch remains on). Note in
the ROM of lines 38-40 that the i rst byte contains the values 0 (last half) and 1
(right half), the second contains 2 and 3, the third contains 4 and 5, and so on, so

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