Hardware Reference
In-Depth Information
Figure 14.8
(a) I 2 C communication principle. (b) Time parameters. (c) Resulting (allowed) operation.
range. It depends on the total
SCL or SDA wire capacitance; if it is large (long bus with many slaves), then the resis-
tor must be small to achieve the rise time dei ned in the I 2 C specii cations. The value
of V DD was 5 V in initial I 2 C-driven devices, but voltages as low as 1.8 V are now
common.
The value of R PU is typically in the 1-k
Ω
to 33-k
Ω
14.2.3 I 2 C Bus Operation
Data transfers are always done one byte at a time, after which an acknowledgment bit
is issued by the receiving end. The general principle is depicted in
i gure 14.8a, which
shows a data transmission from the master to a slave. The start sequence consists of
lowering SDA with SCL high, whereas the stop sequence consists of raising SDA with
SCL high. This means that during data transmission SDA must remain stable while
SCL is high; otherwise start/stop commands will occur (note in the i gure that the data
is always updated while SCL is low). While the master is transmitting (always MSB
i rst), the slave remains with its output high (nMOS transistor cut off—represented by
'Z' in the i gure), so the master has control over the SDA wire. After the eighth bit is
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