Hardware Reference
In-Depth Information
The fourth code section (lines 78-80) is an
always_ff
block that implements the
FSM's state register, again exactly as in the template.
The i fth portion (lines 83-139) of the statements is part of an
always_comb
block
that implements the entire FSM's combinational logic section. It is just a list with all
states, each containing the output and time parameter values, plus the next state.
Observe that in the (originally) recursive equations (lines 96, 104, 113, and 122),
A_reg
appears on the right-hand side instead of
A
itself (as proposed in the template). As
usual, in each state the output values are unique because in a Moore machine the
outputs depend only on the state in which the machine is.
Finally, the code in lines 142-147 implements the test circuit. This code is impor-
tant because it illustrates one way (similar to VHDL—see section 12.6) of dealing with
a bidirectional bus. Note that during the writing procedure the FPGA sends data to
the SRAM, but when data is being read from the SRAM, the FPGA's output must go
into high-impedance (l oating) mode because they (FPGA and SRAM) are physically
connected to the same wires (data bus
D
). Observe also that the generated data consist
simply of
A
+
seed
(line 142; see also
i gure 13.1), which is written to the SRAM when
a
wr
= '1' pulse occurs and is read from the SRAM and displayed on the SSD when a
rd
= '1' pulse occurs.
In this kind of application, glitches during clock transitions are generally not a
problem, so the optional output register is not needed.
Finally, and very importantly, observe the correct use of registers and the complete-
ness of the code, as described in comment 8 of section 7.3. Observe in particular the
following: 1) all states are included; 2) the list of outputs is exactly the same in all
states, and the corresponding values/expressions are always properly declared; 3) the
specii cations for
nx_state
, when conditional, are always i nalized with an
else
state-
ment, so no condition is left unchecked.
1 //Module header:-----------------------------------
2 module sram_interface
3
#(parameter
4
//Main-circuit parameters:
5
Abus = 18, //Address bus width
6
Dbus = 16, //Data bus width
7
//Test-circuit parameters:
8
Tread = 25_000_000, //Time=0.5s @fclk=50MHz
9
Amax = 12) //Max address in test circuit
10
(
11
//Main-circuit ports:
12
input logic rd, wr, clk, rst,
13
output logic CEn, WEn, OEn, UBn, LBn,
14
output logic [17:0] A,
15
//Test-circuit ports:
16
inout logic [7:0] D, //Only lower-byte used
17
input logic [1:0] seed,
18
output logic [6:0] ssd,
19
output logic done_wr, done_rd);
20
