Hardware Reference
In-Depth Information
37
end
38
B: begin
39
outp <= outp_reg + 1;
40
tmax <= T2-1; //if using strategy #2
41
if (condition) nx_state <= C;
42
else if (condition) nx_state <= ...;
43
else nx_state <= B;
44
end
45
C: begin
46
...
47
end
48
...
49
endcase
50
51
//Optional output register:
52
(same as for category 1 Moore, section 7.3)
53
54 endmodule
55 //---------------------------------------------------
13.3 SystemVerilog Template for Recursive (Category 3) Mealy Machines
The template is presented below. The only difference with respect to the Moore tem-
plate just described is in the
always_comb
block for the combinational logic (lines
27-63) because the output is specii ed differently now. Recall that in a Mealy machine
the output depends not only on the FSM's state but also on its input, so
if
statements
are expected for the output in one or more states because the output (and
t
max
) values
might not be unique. This is achieved by including such values
within
the conditional
statements for
nx_state
. For example, observe in lines 29-44, relative to state A, that
the output (and
t
max
) values are now conditional. Compare these lines against lines
31-37 in the previous template.
1 //Part 1: Module header:----------------------------
2
(same as for category 3 Moore, section 13.2)
3
4 //Part 2: Declarations:------------------------------
5
6
//FSM-related declarations:
7
(same as for category 3 Moore, section 13.2)
8
9
//Timer-related declarations:
10
(same as for category 3 Moore, section 13.2)
11
12
//Auxiliary-register-related declarations:
13
(same as for category 3 Moore, section 13.2)
14
15 //Part 3: Statements:-------------------------------
16
17
//Timer:
18
(same as for category 3 Moore, section 13.2)
19
