Hardware Reference
In-Depth Information
13 SystemVerilog Design of Recursive (Category 3) State Machines
13.1 Introduction
This chapter presents several SystemVerilog designs of category 3 state machines. It
starts by presenting two SystemVerilog templates, for Moore- and Mealy-based imple-
mentations, which are used subsequently to develop a series of designs related to the
examples introduced in chapter 11.
The codes are always complete (not only partial sketches) and are accompanied by
comments and often also simulation results, illustrating the design's main features.
All circuits were synthesized using Quartus II (from Altera) or ISE (from Xilinx). The
simulations were performed with Quartus II or ModelSim (from Mentor Graphics).
The default encoding scheme for the states of the FSMs was regular sequential encod-
ing (see encoding options in section 3.7).
The same designs were developed in chapter 12 using VHDL, so the reader can
make a direct comparison between the codes.
Note
: See suggestions of SystemVerilog topics in the bibliography.
13.2 SystemVerilog Template for Recursive (Category 3) Moore Machines
The template is presented below. Because it is an extension to the Moore templates
for categories 1 and 2, described in sections 7.3 and 10.2, respectively, a review of
those templates is suggested before this one is examined because only the differences
are described.
The only differences are those needed for the inclusion of an auxiliary register,
compulsory in category 3 machines. In summary, the following must be added/
done to the previous template: declarations concerning the auxiliary register; an
always_ff
block to infer the auxiliary register; and proper adjustments in the recur-
sive equations to invoke the auxiliary register. These modii cations are described
next.
