Hardware Reference
In-Depth Information
a) Solve parts a and b of exercise 11.3 if not done yet.
b) How many DFFs are needed to build the resulting FSM, with sequential encoding
and
dv
lasting 64 clock periods (so
y
can go from 0 to 64)?
c) Implement your machine using VHDL. Check if the number of DFFs inferred by
the compiler matches your estimate.
d) Recompile the code for
N
= 9 (hence with four bits for
y
) and simulate it using the
same stimuli of i gure 11.17, checking if the same waveforms result.
e) Even though exercise 11.3 is important to understand how that kind of circuit can
be modeled as an FSM, it was said in sections 5.4.1 and 11.7.1 that counters are well-
known circuits, easily designed without the FSM approach. Therefore, because a
Hamming calculator is a kind of counter, it can be designed directly in VHDL. Do it.
Check the number of DFFs and combinational elements needed to implement it for
dv
lasting 64 clock periods and compare the results against those obtained in part
c above.
Exercise 12.4: Leading-Ones Counter
This exercise concerns the leading-ones counter of exercise 11.4.
a) Solve parts a and b of exercise 11.4 if not done yet.
b) How many DFFs are needed to build the resulting FSM, with sequential encoding
and
dv
lasting 64 clock periods (so
y
can go from 0 to 64)?
c) Implement your machine using VHDL. Check if the number of DFFs inferred by
the compiler matches your estimate.
d) Recompile the code for
N
= 9 (hence with four bits for
y
) and simulate it using the
same stimuli of i gure 11.18, checking if the same waveforms result.
e) Even though exercise 11.4 is important to understand how that kind of circuit can
be modeled as an FSM, it is said in sections 5.4.1 and 11.7.1 that counters are well-
known circuits, easily designed without the FSM approach. Therefore, because a
leading-ones counter is a kind of counter, it can be designed directly in VHDL. Do it.
Check the number of DFFs and combinational elements needed to implement it for
dv
lasting 64 clock periods and compare the results against those obtained in part
c above.
Exercise 12.5: Complete Reference-Value Defi ner
Figure 12.4 shows an initial block diagram for the experiment to be developed in this
exercise. It consists of a reference-value dei ner with up-down controls, which must
also include some type of debouncer for the pushbuttons. The output (reference value)
must range from 00 to 60 and must be displayed on two SSDs or an LCD. Note that
ref
is a six-bit signal, while each display digit (
dig0
for units,
dig1
for tens of units) is
a seven-bit value if SSDs are employed. A special feature desired for this circuit is the
