Hardware Reference
In-Depth Information
simply of
seed
+
A
(line 177—see also i gure 12.3), which is written to the SRAM when
a
wr
= '1' pulse occurs and is read from the SRAM and displayed on the SSD when a
rd
= '1' pulse occurs.
In this kind of application, glitches during clock transitions are generally not a
problem, so the optional output register is not needed.
Observe the correct use of registers and the completeness of the code, as described
in comment 10 of section 6.3.
1 ------------------------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 use ieee.std_logic_unsigned.all;
5 use ieee.std_logic_arith.all;
6 ------------------------------------------------------------------
7 entity sram_interface is
8 generic (
9 --Main-circuit parameters:
10 Abus: natural := 18; --Address bus width
11 Dbus: natural := 16; --Data bus width
12 --Test-circuit parameters:
13 Tread: natural := 25_000_000; --Time=0.5s @fclk=50MHz
14 Amax: natural := 12); --Max address in test circuit
15 port (
16 --Main-circuit ports:
17 rd, wr, clk, rst: in std_logic;
18 CEn, WEn, OEn, UBn, LBn: out std_logic;
19 A: out std_logic_vector(Abus-1 downto 0);
20 --Test-circuit ports:
21 D: inout std_logic_vector(7 downto 0); --Lower-byte only
22 seed: in std_logic_vector(1 downto 0);
23 ssd: out std_logic_vector(6 downto 0);
24 done_wr, done_rd: buffer std_logic);
25 end entity;
26 ------------------------------------------------------------------
27 architecture moore_fsm of sram_interface is
28
29
--FSM-related declarations:
30
type state is (idle, write1, write2, read1, read2, hold);
31
signal pr_state, nx_state: state;
32
33
--Auxiliary-register-related declarations:
34
signal addr, addr_reg: natural range 0 to 2**Abus-1;
35
36
--Timer-related declarations:
37
signal t, tmax: natural range 0 to Tread-1; --range≥Tread
38
39
function int_to_ssd(signal input: natural) return std_logic_vector
40
is variable output: std_logic_vector(6 downto 0);
41
begin
42
case input is
43
when 0 => output:="0000001";
44
when 1 => output:="1001111";
45
when 2 => output:="0010010";
