Hardware Reference
In-Depth Information
to indicate when the test circuit has i nished writing to or reading from the memory,
respectively.
The architecture, called
moore_fsm
, is in lines 27-181. As usual, it contains a declara-
tive part and a statements part, with six code sections in the latter.
The architecture's declarative part is in lines 29-62. In the FSM-related declarations
(lines 30-31), the enumerated type
state
is created to represent the machine's present
and next states. In the auxiliary-register-related declarations (line 34), the signals
addr
and
addr_reg
are created to deal with the auxiliary register (observe that the address is
the signal that appears in the recursive expressions, so that is the signal to be stored
in that register). In the timer-related declarations (line 37), the signals needed to build
a 0.5-s timer are created to be used in the
read1-read2
transition (see
t
=
T
2
) of i gure
11.16c, so the user will have enough time to observe the value presented on the display
during the tests. Finally, a function is created in lines 39-62 to later implement the
SSD driver (integer-to-SSD conversion).
The i rst code section (line 67) in the architecture's statements part is a list of static
signals to be connected to the SRAM chip during the tests. Note that they are all
enabled (because they are active low) except for the upper byte of the data word, which
is not used here.
The second code section (lines 70-81) contains a process that implements the timer
(needed in the
read1-read2
transition; the
write1-write2
transition is made at full clock
speed). This code is similar to the template of section 9.2. Both timer control strategies
(section 8.5) are allowed for this FSM.
The third code section (lines 84-91) in the architecture's statements part is a process
that implements the auxiliary register, exactly as in the template.
The fourth code section (lines 94-101) is another process, which implements the
FSM's state register, again exactly as in the template.
The i fth code section (lines 104-172) contains a process that implements the entire
combinational logic section. It is just a list of all states, each containing the output
and time parameter values plus the next state. Observe that in the (originally) recursive
equations (lines 121, 128, 139, and 150),
addr_reg
appears on the right-hand side
instead of
addr
itself (as proposed in the template). As usual, in each state the output
values are unique because in a Moore machine the outputs depend only on the state
in which the machine is.
The sixth and i nal code section (lines 174-179) in the architecture's statements
part passes the value of
addr
to
A
(in
std_logic_vector
form) and also builds the test
circuit. The test circuit is important because it illustrates how we can deal with a
bidirectional bus. Note that during the writing procedure the FPGA sends data to the
SRAM, but when data is being read from the SRAM the FPGA's output must go into
high-impedance (l oating) mode because they (FPGA and SRAM) are physically con-
nected to the same wires (data bus
D
). Observe also that the generated data consist
