Hardware Reference
In-Depth Information
77
y(i-1) <= '1';
78
done <= '0';
79
if i=N then
80
nx_state <= idle;
81
elsif x='0' then
82
nx_state <= store0;
83
else
84
nx_state <= store1;
85
end if;
86
end case;
87
end process;
88
89 end architecture;
90 --------------------------------------------------------
12.6 Design of a Memory Interface
This section presents a VHDL-based design for the memory interface introduced in
section 11.7.8 (i gure 11.16). The SRAM used in the experiments is the IS61LV25616
device, from ISSI, which is capable of storing 262k 16-bit words. The corresponding
FSM was presented in i gure 11.16c, and the circuit ports are depicted in i gure 12.3
(note that a test circuit has been included).
The entity, called sram_interface , is in lines 7-25. Note that several parameters were
declared as generic (lines 8-14), so they can be easily modii ed and overridden. Note
also that the port names are from i gure 12.3 and that all ports (lines 15-24) are of
type std_logic or std_logic_vector (industry standard).
The signals in lines 21-24 are for the test circuit (see i gure 12.3). The signal seed
(line 22), set by two switches, is added to the actual address ( A , line 19) to produce
the test data ( D , line 21), which is displayed on a seven-segment display by means of
the signal ssd (line 23). Two LEDs are lit by the signals done_wr and done_rd (line 24)
Figure 12.3
Setup for the experiments with the SRAM memory interface introduced in i gure 11.16, including
a test circuit as well. The device's truth table is also shown.
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