Hardware Reference
In-Depth Information
21
signal i, i_reg: natural range 0 to N;
22
23 begin
24
25
--Auxiliary register:
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process (clk, rst)
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begin
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if rst='1' then
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i_reg <= 0;
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y_reg
<
= (others =
>
'0');
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elsif rising_edge(clk) then
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i_reg <= i;
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y_reg <= y;
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end if;
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end process;
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--FSM state register:
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process (clk, rst)
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begin
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if rst='1' then
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pr_state <= idle;
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elsif rising_edge(clk) then
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pr_state <= nx_state;
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end if;
45
end process;
46
47
--FSM combinational logic:
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process (all)
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begin
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case pr_state is
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when idle =>
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i <= 0;
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y <= y_reg;
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done <= '1';
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if dv='1' and x='0' then
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nx_state <= store0;
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elsif dv='1' and x='1' then
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nx_state <= store1;
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else
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nx_state <= idle;
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end if;
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when store0 =>
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i <= i_reg + 1;
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y <= y_reg;
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y(i-1) <= '0';
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done <= '0';
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if i=N then
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nx_state <= idle;
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elsif x='1' then
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nx_state
<
= store1;
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else
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nx_state
<
= store0;
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end if;
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when store1 =>
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i <= i_reg + 1;
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y
<
= y_reg;
