VHDL Design of Recursive (Category 3) State Machines - Finite State Machines in Hardware - page 249

32 outp <= outp_reg + 1;

33 tmax <= <value>;

34 nx_state <= ...;

35 else

36 outp <= outp_reg;

37 tmax <= <value>;

38 nx_state <= A;

39 end if;

40 when B =>

41 if <condition> then

42 outp <= outp_reg;

43 tmax <= <value>;

44 nx_state <= C;

45 elsif <condition> then

46 outp <= outp_reg - 1;

47 tmax <= <value>;

48 nx_state <= ...;

49 else

50 outp <= outp_reg;

51 tmax <= <value>;

52 nx_state <= B;

53 end if;

54 when C =>

55 ...

56 end case;

57 end process;

58
59 --Optional output register:

60 (same as for Moore, Section 12.2)

61
62

output <= outp;

63
64 end architecture;
65 -------------------------------------------------------------

12.4 Design of a Datapath Controller for a Multiplier

This section presents a VHDL-based design for the control unit introduced in section
11.7.5, which controls a datapath to produce a sequential add-and-shift multiplier.
The Moore template for category 3 machines seen in section 12.2 is used to implement
the FSM of i gure 11.12b.
The entity, called control_unit_for_multiplier , is in lines 5-11. The number of bits ( N )
in the multiplier and multiplicand was entered as a generic parameter (line 6); a small
value ( N = 4) was used to ease the inspection of the simulation results. Note that all
ports (lines 8-10) are of type std_logic or std_logic_vector (industry standard).
The architecture, called moore_fsm , is in lines 13-93. As usual, it contains a declara-
tive part and a statements part, with three processes in the latter.
The declarative part of the architecture (lines 15-20) contains FSM- and auxiliary-
register-related declarations. In the former the enumerated type state is created to
represent the machine's present and next states. In the latter the signals i and i_reg