Hardware Reference
In-Depth Information
12 VHDL Design of Recursive (Category 3) State Machines
12.1 Introduction
This chapter presents several VHDL designs of category 3 state machines. It starts by
presenting two VHDL templates, for Moore- and Mealy-based implementations, which
are used subsequently to develop a series of designs related to the examples introduced
in chapter 11.
The codes are always complete (not only partial sketches) and are accompanied by
comments and often also simulation results illustrating the design's main features. All
circuits were synthesized using Quartus II (from Altera) or ISE (from Xilinx). The simu-
lations were performed with Quartus II or ModelSim (from Mentor Graphics). The
default encoding scheme for the states of the FSMs was regular sequential encoding
(see encoding options in section 3.7; see ways of selecting the encoding scheme at the
end of section 6.3).
The same designs are presented in chapter 13 using SystemVerilog, so the reader
can make a direct comparison between the codes.
Note
: See suggestions of VHDL topics in the bibliography.
12.2 VHDL Template for Recursive (Category 3) Moore Machines
The template is presented below. Because it is an extension to the Moore templates
for categories 1 and 2, described in sections 6.3 and 9.2, respectively, a review of those
templates is suggested before this one is examined because only the differences are
described. Review also some possible code variations in section 6.4.
The only differences are those needed for the inclusion of an auxiliary register,
compulsory in category 3 machines. As seen in section 6.2, the architecture is com-
posed of two parts, the declarative part (before
begin
) and the statements part
(from
begin
on); both have new elements in order to accommodate the auxiliary
register.
