Hardware Reference
In-Depth Information
Figure 11.18
a) Based on the given data, draw a Moore-type state transition diagram for this
problem. Include a reset signal but assume that it can be asserted only at power-up.
b) Based on your state diagram, i ll in the waveform for
pr_state
in the i gure.
c) Redo part a assuming now that a reset pulse is applied to the FSM before each new
computation starts. Can you i nd a solution with fewer states than in a?
d) Draw an illustrative timing diagram, similar to that in i gure 11.17, for the FSM
developed in part c.
e) How many DFFs are needed to build each machine developed above, assuming that
sequential encoding is used and that
x
is a 32-bit vector (so
y
can go from 0 to 32)?
Exercise 11.4: Leading-Ones Counter
The circuit of i gure 11.18 must count the number of '1's before a '0' is found in a
serial
bit vector
x
. The vector is delimited by a data-valid bit (the counting must occur
during all the time while
dv
= '1'). Study the illustrative timing diagram included in
the i gure. Observe that
dv
and
x
(= “111110000,” so
N
= 9) are updated at positive
clock edges, which are the same edges at which the FSM must operate.
a) Draw a state transition diagram for this machine.
b) Based on your machine, complete the plots for
y
and
pr_state
in the i gure.
c) Say that we want the output value to remain stable (constant) during the computa-
tions, with the current value replaced only when a new value is ready. How can that
be done? (Suggestion: see section 3.11.)
Exercise 11.5: Long-String Comparator
Develop an FSM that detects if two
serial
bit streams
a
and
b
of length
N
are pair-wise
equal. This is an extension to the example of section 11.7.2 in which the FSM had to
detect if the
last N
bits were equal. The circuit ports are depicted in the upper part of
i gure 11.19, which also shows an XNOR gate (
x
= '1' when
a
=
b
). The desired behavior
is also illustrated in the i gure for
N
= 4. Note in the
y
and
done
waveforms that after
every four bits, starting right after the reset pulse,
done
must be asserted, informing
that a complete block has been inspected, with
y
high during that pulse if the four
pairs of bits were equal (
x
= '1' in all four time slots) or low otherwise.
