Hardware Reference
In-Depth Information
Figure 11.16
FSM implementing memory-write and memory-read procedures for an actual 262k
16 SRAM.
(a) Chip pinout. (b) Illustrative timing diagram (here,
wr
and
rd
are short pulses). (c) Correspond-
ing state machine.
×
memory-write cycle). The largest read/write time parameter is 10 ns, so a clock of up
to 100 MHz can be used in the procedure shown in the i gure. Finally, note that the
wr
command lasts just one clock cycle, so the end of writing is determined by a pre-
dei ned maximum address value.
A memory-read procedure is presented in the right half of i gure 11.16b. When the
device is not in write mode (write is done with
WEn
low), it is automatically in read
mode, so when the
rd
command (which also lasts only one clock cycle) occurs, all
that is needed is to do the address sweep.
A complete FSM for writing to (upper branch) and reading from (lower branch) this
device is presented in i gure 11.16c. If a
wr
= '1' pulse occurs, data is written to the
SRAM from address
A
= 0 (or any other initial value) up to
A
=
A
max
. A similar situation
occurs for reading when an
rd
= '1' pulse is received. Note that state
hold
is important
to prevent overwriting or overreading in case
wr
or
rd
is too long. The signals
done_wr
and
done_rd
were included to inform the user when writing or reading has been com-
pleted. Note also the inclusion of
t
=
T
1
and
t
=
T
2
in two of the transitions, which
indicate a way of reducing the write/read speed if that is desired.
A complete design for this memory interface, using VHDL and SystemVerilog, is
presented in sections 12.6 and 13.6, respectively. The number of l ip-l ops is treated
in exercise 11.15.
