Hardware Reference
In-Depth Information
a '1'; otherwise, no subtraction occurs, and the result is shifted to the left with a '0'
in the empty position. After
N
+ 1 iterations, the i nal result will be available. Note
that the actual value of
rem
does not include its LSB.
The algorithm is described in ASM form in
i gure 11.13b. A data-valid bit (
dv
= '1'
during one clock period) is used to tell the circuit when the computation should start.
The algorithm runs
N
+ 1 times (for
i
= 0 to
N
), so when
i
=
N
+ 1 occurs, the algorithm
returns to the beginning, ready to start a new computation when
dv
is asserted again.
As in the previous section, an optional nop (no operation) stage was included in the
left branch to consume one clock cycle, so the computations will always take a i xed
amount of time.
A Moore machine that implements the complete divider is presented in i gure
11.13c (note that
N
= 4 in this example). In the
load
state,
rem
is zeroed and
quot
is
loaded with
num
. If
rem
den
occurs, followed by state
shift1
, responsible for shifting the data one position to the
left with a '1' included in the rightmost position (following VHDL notation, “&”
means concatenation in the expression
rem
=
rem
(2:0) &
quot
(3), meaning that
rem
(3:1)
=
rem
(2:0) and
rem
(0) =
quot
(3); the expression
quot
=
quot
(2:0) & '1' has a similar
meaning). On the other hand, if
rem
≥
den
, the machine moves to state
subtract
, in which
rem
−
den
when the machine is in
load
, it goes through
the
nop
state, followed by state
shift0
, responsible for shifting the result one position
to the left with a '0' included in the rightmost position. Observe the presence of
recursive equations (
quot
=
quot
,
i
=
i
+ 1, etc.) in several states, which characterize a
category 3 FSM.
<
11.7.7 Serial Data Receiver
This section shows another application that can be solved using a category 3 machine.
It consists of a serial data receiver, which must store the received (one bit at a time)
data in a multibit register. Even though this kind of circuit is simple, so it can be
implemented without the FSM approach, we want to see how it can be modeled as
a state machine (recall that we should be able to model any sequential circuit as an
FSM).
The circuit ports are depicted in
i gure 11.14a. The inputs are
x
(serial bit stream),
dv
(data-valid bit, high during only one clock cycle, informing that data storage should
start), plus the conventional clock and reset. The received data must be stored in
y
,
which is an
N
-l ip-l op register. A signal called
done
is also shown, which informs when
the machine is free to receive/store another serial vector.
It will be assumed that the i rst bit of
x
is made available at the same time that
dv
is asserted, which is more difi cult to implement. Because this kind of problem was
already treated in section 3.10, a review of that section is recommended before pro-
ceeding. Indeed, two solutions for this problem were already presented in i gures
3.16c,e, using a timed machine.
