Hardware Reference
In-Depth Information
Figure 11.13
Complete sequential divider. (a) Algorithm. (b) Flowchart. (c) A possible implementation (for
N
= 4).
remainder (
rem
) values. Contrary to the previous section, here a datapath is not
employed, so the machine is a complete divider, not a control unit.
The division algorithm, for unsigned inputs and employing only subtract and shift
operations, is illustrated in i gure 11.13(a). The computations take
N
+1 iterations (after
a data-load operation), where
N
is the number of bits in all four signals (
num
,
den
,
quot
,
rem
). In this example the inputs are
num =
“1101” (= 13) and
den =
“0101” (=
5), so the expected results are
quot
= “0010” (= 2) and
rem
= “0011” (= 3).
Initially, the denominator is stored in a (i xed) register, while the numerator is
loaded into the quotient register, and the remainder is loaded with zeros. The algo-
rithm checks whether
rem
den
; if yes,
den
is subtracted from
rem,
and the entire result
(
rem
and
quot
) is shifted to the left one position with the empty position i lled with
≥
