Hardware Reference
In-Depth Information
Figure 11.12
Sequential add-and-shift multiplier. (a) Datapath. (b) Control unit implementation.
right one position, with carry). The ALU opcode table is assumed to be that included
in the i gure.
The multiplication starts when the control unit receives dv = '1' (during one clock
period), at which time it enables REG1 (by means of wrR1 = '1') to store (at the next
positive clock edge) the multiplicand, and REG2 (by means of ALUop = 0, sel = '1', and
wrR2 = '1') to store zero in prodL and the multiplier in prodR . After this, wrR1 stays low
until the end of the computations, while wrR2 is asserted at the end of each iteration
to enable the storage of ALUout into prodL , after which shift = '1' is produced to shift
REG2 one position to the right. After N of such iterations, the product will be available
in REG2.
A Moore machine that implements the control unit of i gure 11.12(a) is presented
in i gure 11.12(b), which is a direct translation of the algorithm described above.
Observe the inclusion of a wait state, needed for the reason explained in comment 4
at the end of section 3.13.
VHDL and SystemVerilog implementations for this multiplier are presented in sec-
tions 12.4 and 13.4, respectively.
11.7.6 Sequential Divider
This section describes a state machine capable of sequentially computing the division
num / den (numerator/denominator), producing the corresponding quotient ( quot ) and
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