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i gure 11.5c; this is called a synchronous counter with serial enable; for small counters—
typically up to four or i ve bits—parallel enable can be employed, but then no longer
with a standard logic cell).
The nonoptimality mentioned above can be verii ed, for example, by counting the
number of DFFs needed to build the category 3 circuit. Based on section 11.6, and
assuming that x is an eight-bit value and that regular sequential encoding (section
3.7) is used for the FSMs, the number of DFFs is as follows: in i gure 11.5a: 1 for the
two states + 8 for x = 9 DFFs; in i gure 11.5b: 2 for the three states + 8 for x = 10 DFFs;
with category 1: 8 DFFs in either case.
11.7.2 Long-String Comparator
This section deals with an FSM capable of sequentially comparing two arbitrarily long
serial bit streams. The machine must determine whether the last N bits are pairwise
equal (this means that the effect of the oldest pair of bits must be discarded when a
new pair is received). Note that this is very different from determining whether two
sequential blocks of N bits each are equal (in the latter, N bits are compared, then the
next N bits are compared, and so on, without overlapping). The former is described
in this section, and the latter is treated in exercise 11.5.
The circuit ports are depicted in i gure 11.6a. The inputs (serial bit streams) are a
and b , while the output is y (= '1' if all last N pairs of bits are equal). The comparator
in this case is just a two-input XNOR gate, also depicted in the i gure, which produces
x = '1' when the inputs are equal. This signal ( x ) will be the actual input to the FSM.
A corresponding Moore-type solution is presented in i gure 11.6b. Note that
besides the actual output ( y ), it also produces an auxiliary output ( i ) that is a counter
Figure 11.6
Two-string comparator that produces y = '1' if the last N bits are pairwise equal. (a) Circuit ports
and bit comparator. (b) State transition diagram. (c) Illustrative timing diagram, for N = 4.
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