Hardware Reference
In-Depth Information
to represent counters of any size. Even though one does not need the FSM approach
to implement a counter when using an EDA tool (such as VHDL or SystemVerilog),
the formal extension presented here will help in understanding the examples that
follow, which often contain an embedded counter.
Two examples of counters modeled as category 3 FSMs are examined in this section
(where
N
is the number of bits): (a) free-running (meaning that once the last value is
reached it returns and restarts automatically from the initial value) with modulo 2
N
;
(b) free-running with modulo
2
N
.
A modulo 2
N
counter is one that has 2
N
states, thus spanning all possible
N
-bit
values. A regular modulo 2
N
sequential counter will count from 0 to 2
N
<
1, restarting
then automatically from zero. This type of counter is depicted in i gure 11.5a. As usual,
ena
= '1' allows the counter to run, whereas
ena
= '0' causes it to stop. Note the pres-
ence of reset, which acts directly on the
hold
(
x
=
x
) state, thereby being able to set
x
= 0 (or any other value) as the starting value.
A modulo
−
N
states, thus not spanning all
possible
N
-bit values. Therefore, a mechanism for starting/stopping the counter at the
desired values is needed. A category 3 solution for this kind of counter is presented
in i gure 11.5b, where
x
min
and
x
max
represent the counter's initial and i nal values,
respectively.
The examples above show that there is a big difference between category 1 and
category 3 representations for counters. In the former all states are required to appear
in the state transition diagram (section 5.4.1), whereas in the latter only very few states
are needed (i gure 11.5), regardless of the counter's number of states (thus, only the
latter allows large counters to be conveniently represented as state machines). There
is a price to pay, however: even though the resulting circuits in category 1 and category
3 are quite similar, only the former can lead to optimal implementations (similar to
<
2
N
counter is one that has fewer than 2
Figure 11.5
(a, b) Generic counters modeled as category 3 FSMs, free running in the range 0 to 2
N
−
1 or
x
min
to
x
max
, respectively. (c) Usual (optimal) construction for large synchronous counters.
