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is incremented in B and zeroed in A. Finally, counter k , which controls the number
of loops, is incremented in B but is not zeroed in A.
11.6 Number of Flip-Flops
As mentioned earlier, it is difi cult to estimate the number of logic gates that will be
needed in a large design, but it is always possible to determine, and exactly, the
number of l ip-l ops.
In the particular case of sequential circuits implemented as category 3 state
machines, there are four demands for DFFs, as follows:
1) For the state register (below, M FSM is the number of states):
For sequential or Gray encoding: N FSM = log 2 M FSM . Example: M FSM = 25
N FSM = 5.
For Johnson encoding: N FSM = M FSM /2 . Example: M FSM = 25
N FSM = 13.
N FSM = 25.
2) For the auxiliary register (compulsory, for at least one output, total b aux bits):
N aux = b aux . Example: b aux = 8
For One-hot encoding: N FSM = M FSM . Example: M FSM = 25
N aux = 8.
3) For the output register (optional, never needed for outputs processed by auxiliary
registers, total b output bits):
N output = b output . Example: b output = 16
N output = 16.
4) For the timer (optional; category 3 can have all four types of transitions):
N timer = log 2 T max , where T max is the largest transition time, expressed in “number
of clock cycles”; that is, T max = t state_max
f clk , where t state_max is the largest transition
time, in seconds, and f clk is the clock frequency, in hertz.
×
Therefore, the total number of DFFs is N total = N FSM + N aux + N output + N timer . In the
examples that follow, as well as in the actual designs with VHDL and SystemVerilog,
the number of l ip-l ops will be examined often.
11.7 Examples of Recursive (Category 3) State Machines
A series of recursive FSMs are presented next. Several of these examples will be
designed later using VHDL (chapter 12) and SystemVerilog (chapter 13).
11.7.1 Generic Counters
As mentioned in section 5.4.1, counters are well-known circuits, easily designed
without the FSM approach. Nevertheless, because they illustrate the state machine
technique well, an example was included in that section using a regular FSM. A limita-
tion seen there is that only small counters can be represented as regular state machines.
In this section we are interested in examining how the FSM model can be extended
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