Hardware Reference
In-Depth Information
Figure 11.2
Examples of category 3 state machines.
next memory address. Because the expression
addr
=
addr
+ 1 is not a constant but,
rather, depends on the previous value of
addr
, this l owchart cannot be implemented
in hardware without some sort of auxiliary memory (to hold the value of
addr
), which
must be provided along with the corresponding FSM (note that this is different—and
more complex—than a “similar” implementation in software).
The second example (i gure 11.2b) consists of a state machine with three outputs.
Note that the list of outputs is exactly the same in all states (as required for hardware
implementations using the standard architecture; otherwise latches would be inferred),
but again not all output values are deterministic: in state B,
z
must keep the same
value that it had when the machine left state A; in state C,
y
must exhibit the comple-
ment of the value that it had in the previous state, while
z
must be incremented.
Recall that we cannot simply write
z
=
z
A
in state B because
z
A
might have changed;
for the same reason, we cannot write
y
=
y
B
and
z
=
z
A
+ 1 in state C. Consequently,
an extra memory (to hold the values of
y
and
z
) is again needed.
′
11.3 Architectures for Recursive (Category 3) Machines
The general architecture for category 3 machines is summarized in i gure 11.3a. This
representation follows the style of i gures 3.1b and 3.1d, but the style of i gures 3.1a
and 3.1c could be used equivalently. Note that the timer is optional, but at least one
auxiliary register is necessary.
In this illustration, only for the signal that produces
output2
an auxiliary register is
needed, so for that output the optional output register (i gure 11.3b) is never required
(the dashed lines indicate that
output2
can be either the unregistered or the registered
