Hardware Reference
In-Depth Information
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//FSM-related declarations:
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typedef enum logic [1:0] {A, B, C, D} state;
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state pr_state, nx_state;
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logic y;
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//Timer-related declarations:
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const logic [1:0] delay = 3; //any value >1
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logic [1:0] t; //tmax≥delay-1
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17 //Statements:----------------------------------------
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//Timer (strategy #1, adapted):
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always_ff @(posedge clk, posedge rst)
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if (rst) t <= 0;
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else if (pr_state!=nx_state & nx_state!=D) t <= 0;
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else if (pr_state==nx_state & t!=delay-1) t <= t + 1;
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//FSM state register:
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always_ff @(posedge clk, posedge rst)
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if (rst) pr_state <= A;
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else pr_state <= nx_state;
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//FSM combinational logic:
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always_comb
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case (pr_state)
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A: begin
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y <= 1'b0;
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if (~x) nx_state <= B;
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else nx_state <= A;
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end
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B: begin
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y <= 1'b0;
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if (x) nx_state <= C;
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else nx_state <= B;
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end
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C: begin
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y <= 1'b1;
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if (~x & t<delay-1) nx_state <= D;
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else if (~x & t>=delay-1) nx_state <= B;
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else if (x & t==delay-1) nx_state <= A;
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else nx_state <= C;
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end
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D: begin
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y <= 1'b1;
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if (x) nx_state <= C;
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else if (~x & t>=delay-2) nx_state <= B;
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else nx_state <= D;
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end
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endcase
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//Optional output register:-------
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always_ff @(posedge clk)
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y_reg <= y;
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62 endmodule
63 //--------------------------------------------------
