Hardware Reference
In-Depth Information
The i rst part of the code ( module header ) is in lines 1-4. The module's name is trig-
gered_mono . Note that all ports are of type logic .
The second part of the code ( declarations ) is in lines 6-15. In the FSM-related dec-
larations (lines 9-11), the enumerated type state is created to represent the machine's
present and next states; also, a variable called y is dei ned because the optional output
register (which will produce a registered version of y , called y_reg ) is needed here to
remove possible glitches. In the timer-related declarations (lines 14-15), a small value
was used for T (called delay in the code; note delay = 3 in line 14) in order to ease the
inspection of the simulation results.
The third and i nal part of the code ( statements ) is in lines 17-62. It contains four
always blocks, described next.
The i rst always block (lines 20-23) is an always_ff that implements the timer.
Note that the timer is not zeroed when the machine enters state D.
The second always block (lines 26-28) is another always_ff , implementing the
machine's state register, exactly as in the template.
The third always block (lines 31-56) is an always_comb , which implements the
entire combinational logic section. It is just a list of all states, each containing the
output ( y ) value and the next state. Note that in each state the output value is unique
because in a Moore machine the output depends only on the state in which the
machine is.
The fourth and i nal always block (lines 59-60) implements the optional output
register, exactly as in the template. Even though y could come directly from a DFF
(hence glitch-free), that is not guaranteed because it depends on the encoding scheme
used in the machine.
Finally, and very importantly, observe the correct use of registers and the complete-
ness of the code, as described in comment 8 of section 7.3. Observe in particular the
following: 1) all states are included; 2) the list of outputs is exactly the same in all
states, and the corresponding values are properly declared; 3) the specii cations for
nx_state are always i nalized with an else statement, so no condition is left unchecked.
The total number of l ip-l ops inferred by the compiler on synthesizing the code
below, with regular sequential encoding for the machine states, was 5 for T = 3 and
15 for T = 3000.
Simulation results are similar to those in i gure 9.2, where the same circuit was
implemented using VHDL.
1 //Module header:-------------------------------------
2 module triggered_mono (
3
input logic x, clk, rst,
4
output logic y_reg);
5
6 //Declarations:--------------------------------------
7
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