Hardware Reference
In-Depth Information
depending on how this timer is controlled by the FSM, the machine can get stuck in
state A forever). Second, it is more costly (in terms of hardware) to compute non-fully
complementary conditions than otherwise. For example, if VHDL is used, the follow-
ing sections of code could be employed for the three cases in i gure 1.7:
For figure 1.7a:
if t=T-1 then
nx_state <= B
elsif t<T-1 then
nx_state <= A;
end if;
For figure 1.7b:
if t>=T-1 then
nx_state <= B
else
nx_state <= A;
end if;
For figure 1.7c:
if t=T-1 then
nx_state <= B
else
nx_state <= A;
end if;
Note that
else
was used to close the
if
statement in the last two codes, which means
that all conditions are covered and only one comparison is needed. On the other
hand, in the i rst code
elsif
was used instead, so an additional comparison is required;
moreover, it does not cover all input combinations, so latches might be inferred by
the compiler. In summary, the option in i gure 1.7a produces an inferior circuit, and
we still have to pay more for it.
Other common mistakes and problems that can occur while one is designing FSMs
in hardware are described in chapter 4.
1.6 Transition Types
A very important classii cation for the transitions, from a hardware perspective, is
introduced in this section. In section 3.6 this classii cation is used to separate any state
machine into one of three categories, immensely easing its hardware-based design.
The state machine of i gure 1.8a is used to describe the transition types, where
x
is
the actual input,
t
is an auxiliary input generated by a timer, and
y
is the actual output.
This machine contains all four possible types of transitions.
Transition AB
(conditional transition)
depends only on the actual input,
x
. If the machine
is in state A, it must move to state B at the i rst (positive) clock edge that i nds
x
=
x
1
.
Transition BC
(timed transition)
depends only on the timer,
t
. The machine must
stay in state B during exactly
T
1
clock cycles, moving then to state C. An auxiliary
circuit (a timer, which is simply a counter, operating from 0 to
T
1
− 1 in this transition)
must be included in the design. By default, the timer is zeroed every time the FSM
changes state; moreover, the timer is kept stopped at zero in states where it is not
needed (states A and D of i gure 1.8a, for example).
Transition CD
(conditional-timed transition)
is more complex because it depends on
the actual input,
x
, and also on the timer,
t
. The machine must move to state D at
the i rst (positive) clock edge that i nds
x
=
x
2
after staying in state C during
T
2
clock
